Well, at least you admit you're "undercover". Only ole timers on this board, know who I'm talking about, and apparently you do as well

 

Yep I know now...Very perceptive Gen2..

 

Gen 2, are you from the St. Louis area by any chance? You just mentioned names before that led me to consider this...

 

No, I'm Lance, and I live in MS now. That's Mississippi, not Missouri, cyntaxx, lol.

Oh, did I state that I have a Masters Degree in Computer Programming and Engineering? Yeah, but who cares.

 

Cool, please give us a summary of how the chips interface with the EEC memory. Also, please tell us if there are any areas of EEC memory with which chips (any or all) can't interface.

Thanks.

 

Hi Eveyone, I'm Jim from Florida. I have a BS in BS and a PhD in Common Sense. I am married. No kids. I enjoy summers in Rangoon... luge lessons. My father once accused chestnuts of being lazy. For fun we make meat helmets.

Jim

 

More like please give the break down on the new Sledgehammer with the northbridge built into the die of the cpu. Latency specs with ddr400 spec and hypertransport please.

 

Why do I need to do that? It's all right here:

http://www.mindshare.com/hypertransp...ooks_main.html

Just like the chip versus flash debate is right here in this book:

http://www.kotzigpublishing.com/0971541132.php

 

Not links.. provide your expertise on the subject matter.

I dont want theoritical scaling.

 

Low blow...

Jim

 

This p*ssing content needs to end or taken somewhere else. We're getting tired of it. If people want to discuss this topic without resorting to personal attacks and fully revealing their association and agenda with the topic, go ahead. Otherwise the threads that go astray will be removed.